Conventional technologies to configure and manufacture high voltage semiconductor power devices are still confronted with difficulties and limitations to further improve the performances due to different tradeoffs. In vertical semiconductor power devices, there is a tradeoff between the drain to source resistance, i.e., on-state resistance, commonly represented by RdsA (i.e., drain-source resistance×Active Area) as a performance characteristic, and the breakdown voltage sustainable by the power device. A commonly recognized relationship between the breakdown voltage (BV) and the RdsA is expressed as: RdsA is directly proportional to BV2.5. For the purpose of reducing the RdsA, an epitaxial layer is formed with a higher dopant concentration. However, a heavily doped epitaxial layer also reduces the breakdown voltage sustainable by the semiconductor power device.
Several device configurations have been explored in order to resolve the difficulties and limitations caused by these performance tradeoffs. An early attempt to improve breakdown voltage was disclosed in U.S. Pat. No. 4,941,026 to Temple. The Temple device uses a deep trench filled with a gate electrode and lined with a thick oxide. This type of structure allows for greater depletion and therefore the doping concentration of the drift region can be increased. With a higher doping concentration, a lower RdsA can be achieved. However, this structure shifts the burden of supporting nearly all of the voltage to the oxide layer that lines the trench. Increasing the thickness of the oxide in order to support more voltage also increases the stress in the device. Therefore, the BV is limited to lower voltage devices such as those rated below 200V.
FIG. 1 shows the cross section of a conventional floating island and thick bottom trench oxide metal oxide semiconductor (FITMOS) field effect transistor (FET) implemented with thick bottom oxide in the trench gate and floating P-dopant islands under the trench gate to improve the electrical field shape. The charge compensation of the P-dopant in the floating islands allows for the N-epitaxial doping concentration to be increased, thus reduce the RdsA. In addition, the thick bottom oxide in the trench gate lowers the gate to drain coupling, thus lowering the gate to drain charge Qgd. The device further has the advantage of supporting a higher breakdown voltage on both the top epitaxial layer and the lower layer near the floating islands. However, the presence of floating P-region causes higher dynamic on resistance during switching.
In U.S. Pat. No. 7,291,894, Sapp et al. disclose a power transistor that maintains a high BV, while reducing the gate to drain capacitance (Cgd). In the Sapp transistor Cgd is decreased by replacing the trench electrode with an oxide. In order to compensate for the decrease in BV resulting from the removal of the electrode, the walls of the trenches are doped with a P-type dopant before the oxide is formed. This P-doped area provides a charge balancing mechanism that allows for the recovery of some of the BV that was lost by removing the trench electrode, but it is necessary to achieve accurate charge balance to sustain the high breakdown. Similarly, the device described in U.S. Pat. No. 6,762,455 to Oppermann et al also employs a trench filled with oxide. In the Oppermann device the trench sidewall can be doped like that of Sapp, but Oppermann further describes a lower P-doped region being formed below the trench. However, this too suffers from the same limitations as the Sapp device. The absence of an electrode within the trenches places a stringent burden on accurate charge balance to achieve high breakdown.
In U.S. Pat. No. 5,637,898, Baliga discloses a power transistor designed with the specific goal of providing a high breakdown voltage and low on-state resistance. The Baliga power transistor is a vertical field effect transistor in a semiconductor substrate that includes a trench having a bottom in the drift region and an insulated gate electrode for modulating the conductivity of the channel and drift regions in response to the application of a turn-on gate bias. The insulated gate electrode includes an electrically conductive gate in the trench and an insulating region which lines a sidewall of the trench adjacent the channel and drift regions. The insulating region has a non-uniform cross-sectional area between the trench sidewall and the gate. This enhances the forward voltage blocking capability of the transistor by inhibiting the occurrence of high electric field crowding at the bottom of the trench. The thickness of the insulating region is greater along the portion of the sidewall which extends adjacent the drift region and less along the portion of the sidewall which extends adjacent the channel region. The drift region is also non-uniformly doped to have a linearly graded doping profile that decreases in a direction from the drain region to the channel region to provide low on-state resistance. The charge compensation in this device is achieved by the gate electrode. However, the presence of a large gate electrode significantly increases the gate to drain capacitance of this structure, resulting in higher switching losses. In addition, the Baliga device presents the additional manufacturing complexity of having a linearly graded doping profile in the drift region.
In U.S. Pat. No. 7,335,944, Banerjee et al. disclose a type of transistor that includes first and second trenches defining a mesa in a semiconductor substrate. The first and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members separated from the mesa by a thick dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section, i.e., the doping profile gradient in the drift region varies as a function of the vertical depth of the drift region. Each field plate is electrically connected to the source electrode. In this device, the charge compensation is achieved by the field plate connected to the source. However, the manufacturing of this structure requires complex fabrication processes that include deep trenches, thick liner oxide, and a doping concentration gradient.
U.S. Pat. No. 7,649,223 to Kawashima discloses a partial superjunction device-. Superjunction transistors provide a way to achieve low RdsA while maintaining a high BV. Superjunction devices include alternating P-type and N-type doped columns formed in the drift region. In the OFF-state of the MOSFET, the columns completely deplete at relatively low voltage and thus can sustain a high breakdown voltage. In the Kawashima device, the P-doped columns are formed part way into the depth of an N-doped epitaxial layer in which MOSFET device structures are formed. For a superjunction, the RdsA increases in direct proportion to the BV, which is a much less dramatic increase than in the conventional semiconductor structure. However, superjunction devices require complex processing and many additional masking steps, and therefore are expensive to produce.
For the above reasons, there is a need to provide new device configurations and new manufacturing methods for the semiconductor power devices which reduce the on-state resistance and in the meantime increasing the breakdown voltage sustainable by the power device such that the above discussed difficulties and limitations can be resolved.